1. Field of the Invention
The embodiments discussed herein relate to a semiconductor device.
2. Description of the Related Art
Conventionally, to stably secure a high breakdown voltage, a field plate (FP) is often included in an edge termination structure portion of a high voltage diode, a high voltage metal oxide semiconductor field effect transistor (MOSFET), and the like. A resistive field plate (RFP) and a multiple floating field plate (MFFP) are known as field plate structures.
The resistive field plate includes a thin-film resistive layer provided in a spiral planar layout that surrounds the periphery of a high-potential-side region to span from the high potential side (high side) region to a low potential side (low side) region, and the surface potential thereof is controlled using resistance division (see Japanese Laid-Open Patent Publication Nos. 2000-022175 and 2003-008009, International Patent Publication No. 2003-533886, Japanese Laid-Open Patent Publication No. 2000-252426, and Japanese Patent Publication No. 5748353). The multiple floating field plate includes floating coupled capacitance between metal layers provided in a planar layout of concentric circles surrounding the periphery of the high-potential-side region and in multiple layers (multi-ply) through an interlayer insulating film, and the surface potential thereof is controlled using serial junctions of capacitance. In particular, the resistive field plate has a strong compelling force for the surface potential compared to that of the capacitance-coupling multiple floating field plate and is useful for securing a high breakdown voltage.
Even in a case where the resistive field plate includes one spiral thin-film resistive layer, when the thin-film resistive layer is provided to spread in the edge termination structure portion, the intensity of the electric field of the edge termination structure portion is in principle maintained to be uniform by the resistive field plate. When the surface area of the edge termination structure portion is large, etc., the resistance value of the overall resistive field plate may become excessively high. A merit is that current consumption decreases as the resistance value of the overall resistive field plate increases while a demerit is that, when the resistance value of the overall resistive field plate is excessively high, substantially no current flows through the resistive field plate and the compelling force for the surface potential is lost.
When compelling force for the surface potential by the resistive field plate cannot be obtained, for example, mobile ions trapped (captured) in the interlayer insulating film adversely affect the electric field distribution, making uniform electric field distribution difficult to be maintained in the edge termination structure portion. When the thin-film resistive layer constituting the resistive field plate is formed by polysilicon (poly-Si) or the like, the resistance of the resistive field plate may be reduced by increasing the dose amount of the impurity in the polysilicon. This increase of the dose amount of the impurity in the polysilicon is however not practical in cases where a thin-film resistive layer constituting the resistive field plate and the constituent units each including polysilicon in other circuit regions are concurrently formed.
The configuration of a conventional resistive field plate will be described. FIGS. 17, 18A, 18B, and 19 are plan diagrams of the planar layout of a conventional resistive field plate. In FIGS. 17 to 19, the same constituent units are denoted by the same reference numerals. FIG. 17 is “FIG. 6 in Japanese Laid-Open Patent Publication No. 2000-022175”. The resistive field plate depicted in FIG. 17 includes two thin-film resistive layers 103a and 103b that are provided each in a spiral planar layout surrounding a high-potential-side region 101, from the high-potential-side region 101 to a low-potential-side region 102, and that are provided not to intersect each other. Compared to a case where one thin-film resistive layer having an equal overall length is used, the overall length of each single layer of the thin-film resistive layers 103a and 103b is shorter and the surface potential is controlled by the combined resistance thereof.
FIGS. 18A and 18B are “FIG. 1 in Japanese Laid-Open Patent Publication No. 2003-008009”. The depicted resistive field plate includes plural metal layers 113 provided in a planar layout of concentric circles surrounding a high-potential-side region 101, and thin-film resistive layers 114 that each electrically connects the adjacent metal layers 113. A reference numeral “112” denotes a contact (a connecting portion) between the metal layer 113 and the thin-film resistive layer 114. The convenience of the layout is enhanced by providing the metal layers 113 in multiple layers on the thin-film resistive layer 114 through an interlayer insulating film 115. In addition, the length of the thin-film resistive layer 114 is increased to reduce the sheet resistance of the thin-film resistive layer 114 by providing the thin-film resistive layer 114 in a planar layout on a straight line oblique to the orientation of the periphery of the metal layer 113 (FIG. 18B).
FIG. 19 is “FIG. 11 in International Patent Publication No. 2003-533886”. The resistive field plate depicted in FIG. 19 has the ends thereof positioned on the side of a high-potential-side region 101 and on the side of a low-potential-side region 102, and includes two thin-film resistive layers 123a and 123b each provided in a meandering planar layout. The ends of the thin-film resistive layers 123a and 123b in the high-potential-side region 101 are electrically connected to another thin-film resistive layer 124 provided in the high-potential-side region 101. Reference numerals “126a” and “126b” respectively denote metal wires that electrically connect ends on the side of the high-potential-side region 101 of the thin-film resistive layers 123a and 123b to the other thin-film resistive layer 124. Reference numerals “127a” and “127b” denote metal wires that respectively connect ends on the side of the low-potential-side region 102 of the thin-film resistive layers 123a and 123b to a control/evaluating circuit 128.
In the resistive field plate depicted in FIG. 19, the resistance value is reduced to be low compared to that in a case where the thin-film resistive layer is provided in one spiral planar layout, by realizing the function of the resistive field plate using the thin-film resistive layers 123a, 123b, and 124. The thin-film resistive layers 123a and 123b are provided for protruded portions thereof formed corresponding to the meandering cycle to face each other, and a peak of the intensity of the electric field or increase of the electric field is prevented near the protruded portions (hereinafter, each referred to as “protruded portion on the outer side”) on the side not to facing each other. The protruded portions on the outer side of each of the thin-film resistive layers 123a and 123b are connected to each other by a polysilicon tape 125 that surrounds the periphery of the high-potential-side region 101, and the polysilicon tape 125 stabilizes the surface potential.
Japanese Laid-Open Patent Publication No. 2000-252426 discloses a resistive field plate that has a configuration having one thin-film resistive layer provided in a planar layout to meander on a field insulating film covering a field limiting ring (FLR). In Japanese Laid-Open Patent Publication No. 2000-252426, the electric field applied to the field insulating film is mitigated by substantially equalizing the electric field applied to the field limiting ring and the electric field applied to the resistive field plate.
Japanese Patent Publication No. 5748353 discloses a resistive field plate that has a configuration formed by dividing an edge termination structure portion into plural sections and providing different thin-film resistive layers each in a meandering planar layout on a divided section. In Japanese Patent Publication No. 5748353, the edge termination structure portion is provided in a planar layout having a shape including straight line-like portions facing each other and arch portions connecting the ends of the straight line-like portions with each other at the ends thereof. The resistance value of the overall resistive field plate is reduced by providing different thin-film resistive layers on the straight line-like portions having different lengths in the radial direction and the arch portions.